Data Converters

Industrial Technology Research Institute, Hsinchu, Taiwan Since the front-end T/H stage and the two buffers are out of the calibration loop, it is crucial for them to maintain better-than-8b linearity at 600MS/s. A pseud

low-power high-speed ADCs to convert RF/IF signals into digital form for subsequent baseband processing. Considering latency and conversion speed, flash ADCs are often the most preferred option. Generally, flash ADCs suf

T. Hoehn1, P. Schmitz1, H. Werker1, A. Glenny3 National Semiconductor, Unterhaching, Germany National Semiconductor, Greenock, United Kingdom 3 National Semiconductor, Santa Clara, CA 1 2 correct stage N-1’s decision, re

high-speed communication systems, such as serial links, UWB, and OFDM-based 60GHz receivers. Due to complex DSP and low-power constraints, digital basebands are designed in low-leakage, high-VT low-power (LP) CMOS proces

E. Ayranci2, X. Liu2, K. Bult2 Broadcom, Irvine, CA Broadcom, Bunnik, Netherlands 1 2 A 12b 2.9GS/s current-steering DAC implemented in 65nm CMOS is presented, with an IM3 <-60dBc beyond 1GHz while driving a 50Ω load wit

Microsensor wireless networks and implanted biomedical devices have emerged as exciting new application domains. These applications are highly energy constrained and require flexible, integrated, energy-efficient ADC mod

Subranging ADCs meet these requirements by using simple open-loop amplifiers [1, 2]. However, the large number of parallel connected differential amplifiers (pre-amps) and comparators create a bottleneck, making it diffi

The fixed sampling and clock rates in conventional DSPs result in power dissipation determined by the highest frequency to be processed. If sampling and clock are eliminated, one has a DSP operating in continuous-time [1

Infineon Technologies, Munich, Germany Technical University Munich, Munich, Germany 2 Time-to-digital converters (TDC) support the industry wide trend of replacing mixed-signal functionality by digital realizations. High

demand high-resolution high-speed low-voltage ADCs. Pipelined ADCs are well suited for these applications. However, traditional designs of such high-resolution ADCs rely on high-gain operational amplifiers along with goo

Robert Gibbins1, Yuriy Greshishchev1, Naim Ben-Hamida1, Daniel Pollex1, John Sitch1, Shing-Chi Wang1, John Wolczanski1 1 Nortel, Ottawa, Canada STMicroelectronics, Crolles, France 2 New receivers for 10-to-40Gb/s optical

widely used in serial links, magnetic recording systems and UWB receivers. Flash ADCs have been dominantly used for these applications. This paper presents an ADC that takes advantage of the high-speed digital logic and

Finite opamp gain and output swing are two limitations for precision analog circuits. These limitations are especially serious at lower supply voltages where limited headroom prevents the use of cascode devices to improv

accomplished at the cost of analog design features. The prediction of the ITRS roadmap [1] shows a dramatic increase of flicker noise in new technologies. On the other hand, the voltage supply is reduced to almost 1V. Th

University of California, San Diego, CA Conexant, Palm Bay, FL 2 In the digital wireless SoC applications, CT ΔΣ ADCs have been widely used for I/Q quantization due to the built-in anti-aliasing function and insensitivit

bandwidth and high dynamic range. In such systems, a pipeline ADC requires a low-noise high-speed input buffer to drive the sampling capacitor and a sophisticated anti-aliasing filter whereas a CT ΔΣ ADC has an easy-to-d

11n/WiMAX receivers (20 to 2.5MHz per I/Q) is presented. The intent is to replace complex analog baseband circuits with a combination of tunable one-pole filter, anti-alias filter and coarse VGA (Fig. 27.5.1) [1]. Blocke

Kaoru Takasuka2, Seiji Takeuchi2, Gabor C. Temes1 1 Oregon State University, Corvallis, OR, 2Asahi Kasei, Atsugi, Japan Wideband high-resolution ΔΣ ADCs with low power consumption are needed in many wired and wireless co

Feature-size scaling [1] of modern CMOS technologies dictated by Moore’s law enables integration of extensive digital signal processing at low power consumption and small area. As the area of digital functions scales wit

Low-voltage low-power ΔΣ modulators are required for many portable systems. Although SC ΔΣ modulators provide reliable high-resolution A/D conversion, the traditional SC circuit design faces many challenges as the fabric

use 2-level (+1, -1) unit elements in either switched-capacitor or current-steering form. This paper presents a low-power audio DAC that uses a 3-level current-steering unit element architecture. When compared to the 2-l

IMEC, Leuven, Belgium Vrije Universiteit Brussel, Brussel, Belgium 2 High-speed low-resolution ADCs are an essential part of receivers for wireless standards such as UWB. These converters have to combine the stringent sp

Applications using broadband digital wireless modulation require high-resolution low-power ADC over a bandwidth of few megahertz. For a WiFi or a WiMAX standard, an ADC of ~10b resolution in 5 to 20MHz bandwidth is neede

University of Texas, Austin, TX, 2National Semiconductor, Salem, NH Low-power consumption is a key specification in many electronic systems, such as wireless communication and imaging systems. One of the most efficient w

The signal bandwidth used in portable or autonomous sensor systems is often lower than 50kHz with ADC requiring about 8 to 10 bits resolution, but the consumed power must be very low: few μW or a FOM = P/(2ENoBfsampl) lo

Future systems powered by energy scavenging, e.g., wireless sensor nodes, demand μW-range ADCs with no static bias currents in order to have a power dissipation proportional to the sample rate. An ADC that meets these re

in medium- to high-speed (10s of MS/s to a few GS/s) and medium- to low-resolution (4b to 9b) A/D converters. Current state-of-the-art FOM is 65fJ [1]. These efficiency improvements are primarily driven by mobile, wirele

to the highest combination of resolution and speed in pipelined ADCs [1,2] and has made the sampling rate of SAR ADCs competitive with flash ADCs [3,4], but several challenges exist. As every sample must be accurate, per

battery-powered devices demand the adoption of cheap and power-efficient ADCs. SAR architectures have been recently demonstrated as able to achieve high power efficiency in the moderate-resolution/mediumbandwidth range [