A 12b 2.9GS/s DAC with IM3 <-60dBc Beyond 1GHz in 65nm CMOS

📋 论文概要

该论文提出了一款采用65nm CMOS工艺实现的12位2.9GS/s电流舵数模转换器(DAC)，其在1GHz以上频率实现了IM3<-60dBc，同时驱动50Ω负载并输出2.5Vpp差分摆幅，功耗仅为188mW。解决了高速DAC在高频下线性度与功耗的平衡问题。

💡 主要创新点

• 通过创新的电流源开关架构，在65nm CMOS工艺下实现了2.9GS/s的高采样率与超过1GHz的低IM3失真。
• 在保持高输出摆幅(2.5Vpp-diff)和低功耗(188mW)的同时，实现了60dB以上的SFDR(在2.9GS/s且>340MHz频率下)。

🏷 关键词

📄 原文摘要

E. Ayranci2, X. Liu2, K. Bult2 Broadcom, Irvine, CA Broadcom, Bunnik, Netherlands 1 2 A 12b 2.9GS/s current-steering DAC implemented in 65nm CMOS is presented, with an IM3 <-60dBc beyond 1GHz while driving a 50Ω load with an output swing of 2.5Vpp-diff and dissipating a power of 188mW. The SFDR measured at 2.9GS/s is better than 60dB beyond 340MHz. The current-steering DAC depicted in Fig. 4.1.1 on the left side consists of a number of current sources that are switched either to the left or to the right output node, depending on the digital input code. Although the circuit is conceptually very simple, there are numerous error mechanisms that can cause nonlinearities, many of which are described in the literature [1-5]. For low frequencies, some of the dominant effects are the matching of the current sources and IR drops in the supply lines. This requires large-sized current-source transistors and careful layout of the supplies. Another effect that

👥 作者与机构

C-H. Lin1, F. van der Goes2, J. Westra2, J. Mulder2, Y. Lin2, E. Arslan2,