A 5b 800MS/s 2mW Asynchronous Binary-Search ADC in 65nm CMOS

📋 论文概要

该论文提出了一种5位800MS/s的异步二进制搜索ADC，采用65nm CMOS工艺，功耗仅2mW。它解决了传统flash ADC功耗大、面积大和SAR ADC转换速度慢的问题，实现了高速低功耗的模数转换。

💡 主要创新点

• 提出异步二进制搜索结构，结合了SAR的低功耗和flash的高速，单周期内完成所有比较。
• 采用异步控制逻辑，无需高速时钟，降低功耗和设计复杂度。
• 实现了5位分辨率下800MS/s的转换速度，功耗仅2mW，优值领先。

🏷 关键词

📄 原文摘要

low-power high-speed ADCs to convert RF/IF signals into digital form for subsequent baseband processing. Considering latency and conversion speed, flash ADCs are often the most preferred option. Generally, flash ADCs suffer from high power consumption and large area overhead. On the contrary, SAR ADCs have low power dissipation and occupy a small area. However, a SAR ADC needs several comparison cycles to complete one conversion, which limits its conversion speed. The highest single-channel operation speed of previously reported SAR ADCs is 625MS/s [1]. The ADC in [1] utilizes a 2b/step structure. For non-multi-bit/step SAR ADCs, the highest reported conversion rate is 300MS/s [2]. The structure of a comparator-based binary-search ADC is between that of flash and SAR ADCs [3]. Compared to a

👥 作者与机构

Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guang-Ying Huang

National Cheng-Kung University, Tainan, Taiwan Digital wireless communication applications such as UWB and WPAN necessitate