A 600MS/s 30mW 0.13µm CMOS ADC Array Achieving Over 60dB SFDR with Adaptive Digital Equalization

📋 论文概要

该论文提出一个基于0.13μm CMOS工艺的600MS/s ADC阵列，通过自适应数字均衡技术实现超过60dB SFDR，同时功耗仅30mW。解决了高速交织ADC中通道失配引起的SFDR下降问题。

💡 主要创新点

• 采用自适应数字均衡技术动态校正通道失配，无需额外模拟校准回路。
• 利用伪差分顶板采样器和虚设开关/复制阱偏置技术提升前端THA线性度至8位以上。
• 通过双源极限随器分别驱动参考ADC和交织ADC，消除共享驱动带来的串扰。

🏷 关键词

📄 原文摘要

Industrial Technology Research Institute, Hsinchu, Taiwan Since the front-end T/H stage and the two buffers are out of the calibration loop, it is crucial for them to maintain better-than-8b linearity at 600MS/s. A pseudo-differential topology is utilized as shown in Fig. 4.5.3. The top-plate sampler is designed to achieve a 3dB bandwidth of 2.5GHz. Dummy switch and replica well-bias techniques are adopted to improve the THA linearity. Since the reference ADC always samples at the same time as one of the interleaved ADCs, driving them with two separate source followers effectively eliminates any potential interference. 1 2 At high conversion speed, time interleaving provides a viable way of achieving analog-to-digital conversion with low power consumption, especially when

👥 作者与机构

Wenbo Liu1, Yuchun Chang1,2, Szu-Kang Hsien1,3, Bo-Wei Chen3,

Yung-Pin Lee3, Wen-Tsao Chen3, Tzu-Yi Yang3, Gin-Kou Ma3, Yun Chiu1 University of Illinois, Urbana-Champaign, IL Jilin University, Changchun, China 3