A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP Digital CMOS

📋 论文概要

该论文提出了一种在45nm LP数字CMOS工艺下实现的1.1V、50mW、2.5GS/s、7位时间交织C-2C SAR ADC，解决了高速通信系统中低功耗、高采样率ADC的设计挑战。通过时间交织结构和C-2C电容阵列，实现了高能效和高速度的模数转换。

💡 主要创新点

• 采用时间交织C-2C SAR架构，在低功耗数字CMOS工艺中实现2.5GS/s的高速采样。
• 利用金属指状电容（MFC）的匹配和密度优势，提升ADC的线性度和能效。

🏷 关键词

📄 原文摘要

high-speed communication systems, such as serial links, UWB, and OFDM-based 60GHz receivers. Due to complex DSP and low-power constraints, digital basebands are designed in low-leakage, high-VT low-power (LP) CMOS processes making the design of high-speed ADCs challenging. Time-Interleaved (TI) Successive-Approximation-Register-based (SAR) ADCs[1] are ideally suited to these applications due to their highly scalable architecture and due to the steady improvement in matching and density of Metal-Finger Capacitors (MFC). This paper presents a TI C-2C SAR ADC that achieves high performance by using: 1) a small-area C-2C SAR architecture with low input capacitance; 2) high-speed boosted switches to overcome high device threshold; 3) background comparator offset calibration and radix calibration; and 4) redundant-ADC-based gain, offset and timing calibration to reduce

👥 作者与机构

Erkan Alpman1,2, Hasnain Lakdawala1, L. Richard Carley2, K. Soumyanath1

Intel, Hillsboro, OR Carnegie Mellon University, Pittsburgh, PA 1 2 High-speed medium-resolution ADCs are widely utilized in