⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种1.8V、1.0GS/s、10位自校准统一折叠插值ADC，通过嵌入比较器并利用自校准技术校正前级判决，实现了9.1 ENOB的奈奎斯特频率性能，同时减少了比较器数量并抑制了闪烁码。
T. Hoehn1, P. Schmitz1, H. Werker1, A. Glenny3 National Semiconductor, Unterhaching, Germany National Semiconductor, Greenock, United Kingdom 3 National Semiconductor, Santa Clara, CA 1 2 correct stage N-1’s decision, resulting in excellent differential linearity and complete sparkle suppression while requiring only relaxed comparator accuracy, since the RTI gain at the final comparators exceeds 5000. Embedding comparators also reduces their total number. In our previous 8b ADC, there are 43 comparators; for this 10b design there are only 20 comparators (3 for each folding stage, plus 2 at stage 0, the non-folded first flash stage). This cascaded architecture is most efficient for folding-by-3, producing a base-3 result. The encoder complexity is high due to the error correction, which can ripple from the last stage back to the first, and the required base-3-to-base-2 conversion. An advance in folding-interpolating ADCs is presented that simplifies their
R. C. Taft1, P. A. Francese1, M. R. Tursi1, O. Hidri1, A. MacKenzie2,