A 130mW 100MS/s Pipelined ADC with 69dB SNDR Enabled by Digital Harmonic Distortion Correction

📋 论文概要

该论文提出了一种100MS/s、130mW的流水线ADC，通过集成的数字后台谐波失真校正(HDC)和DAC噪声消除(DNC)技术，实现了69dB的SNDR。首次IC实现HDC，有效补偿了残差放大器的增益误差和非线性，以及DAC电容失配，从而在降低功耗方面优于传统流水线ADC。

💡 主要创新点

• 首次在IC中实现数字谐波失真校正(HDC)，用于补偿残差放大器的增益误差和非线性。
• 集成DAC噪声消除(DNC)技术，补偿DAC电容失配。
• 通过HDC和DNC的组合，实现了在相同性能下相比传统流水线ADC更低的功耗。

🏷 关键词

📄 原文摘要

A pipelined ADC is presented with 2 fully integrated digital background calibration techniques: harmonic distortion correction (HDC) to compensate for residue amplifier gain error and nonlinearity, and DAC noise cancellation (DNC) to compensate for DAC capacitor mismatches [1,2]. It is the first IC implementation of HDC, and the results demonstrate that HDC and DNC together enable reductions in power dissipation relative to comparable conventional state-of-the-art pipelined ADCs. HDC is one of two recently proposed techniques that digitally measure and cancel ADC errors caused by residue-amplifier distortion to permit higher-distortion and, thus, lower-power residue amplifiers in pipelined ADCs [1,3]. The benefit of HDC relative to the technique of [3] is that it works for any pipelined ADC input signal [1]. It requires an increase in the resolution of the DAC in each pipeline stage to which it is applied, but as described below this is

👥 作者与机构

Andrea Panigada, Ian Galton

University of California, San Diego, CA