A 5.37mW 10b 200MS/s Dual-Path Pipelined ADC

📋 论文概要

提出一种双路径流水线ADC架构，将残差放大分为粗放大和精放大两步，粗放大器产生大摆幅但精度低，精放大器补偿误差产生小摆幅输出，从而降低运放增益和速度要求，实现了5.37mW、10位、200MS/s的低功耗设计。

💡 主要创新点

• 提出双路径残差放大方案，利用粗放大器与精放大器分离实现高精度放大，同时降低了对运放直流增益和速度的要求。
• 粗放大器采用低功耗开环结构产生大摆幅信号，精放大器仅需处理小摆幅误差，整体功耗显著降低。

🏷 关键词

📄 原文摘要

The opamps in a switched-capacitor (SC) pipelined ADC provide the functions of sample-and-hold, residue generation, and residue amplification [1,2]. High-performance opamps that meet the requirements for dc gain, speed, and signal range usually consume large power. We propose a scheme where the residue amplification is performed first by a coarse amplifier (CA), and then by a fine amplifier (FA). The CA generates a large-swing output that may not be accurate due to low dc gain and slow speed. Subsequently, the FA produces a smallswing output that stands as the error of the CA. The requirements for the CA and FA are different. They can be designed and optimized separately, resulting in low power dissipation. We report a 10b SC pipelined ADC to demonstrate this technique. Fabricated in 65nm CMOS, this ADC achieves 56.7dB SNDR at 200MS/s sampling rate, and consumes 5.37mW from a 1V supply. Figure 27.3.1 shows the ADC architecture. It consists of 8 pipeline stages. Each

👥 作者与机构

Yun Chai, Jieh-Tsorng Wu

National Chiao Tung University, Hsinchu, Taiwan