A 10b 500MHz 55mW CMOS ADC

📋 论文概要

针对单通道ADC在高速采样下的速度瓶颈以及交错架构高功耗或低SNDR的问题，提出一种校准技术结合高速运放拓扑，实现单通道500MHz采样、10位分辨率，对233MHz输入信号达到53dB SNDR，功耗仅55mW，FOM为0.3pJ/conversion-step。

💡 主要创新点

• 提出一种校准技术，有效补偿高速ADC中的非理想因素，提升线性度。
• 设计一种高速运放拓扑，支持500MHz单通道采样同时保持低功耗。
• 在未采用交错结构的情况下，实现与交错架构相当甚至更优的功耗效率。

🏷 关键词

📄 原文摘要

Recent work on ADCs targeting sampling rates of hundreds of MHz with resolutions in the range of 10 to 11b has faced speed limitations with a single channel [1] or employed interleaving, but with a relatively high power dissipation [2] or low SNDR [3]. This paper introduces a calibration technique that, together with a high-speed opamp topology, allows a single channel to operate at 500MHz and digitize a 233MHz input with an SNDR of 53dB. This SNDR yields a figure of merit (FOM) of 0.3pJ/conversion-step, the lowest reported for 10 and 11b ADCs running at these frequencies. Figure 4.6.1 shows the pipelined ADC architecture. It consists of thirteen 1.5b stages and one 1b stage. The ADC also incorporates an on-chip reference DAC for calibration. The first 2 stages are calibrated for capacitor mismatch, opamp gain error, and opamp nonlinearity; the next 4 stages for capacitor mismatch and opamp gain error; and the next 7 stages for opamp gain error. In Fig.

👥 作者与机构

Ashutosh Verma, Behzad Razavi

University of California, Los Angeles, CA