A 16b 125MS/s 385mW 78.7dB SNR CMOS Pipeline ADC

📋 论文概要

本文提出了一款16位125MS/s的流水线ADC，在1.8V供电下功耗仅385mW，实现了78.7dB SNR和96dB SFDR。通过优化电路架构和采用dithering技术，该ADC在保持高精度的同时支持高达150MHz的IF采样，并有效抑制了杂散分量。

💡 主要创新点

• 通过低功耗设计技术实现了16位125MS/s流水线ADC仅385mW的功耗。
• 采用dithering技术显著改善了较小输入信号下的线性度，使得最差杂散低于-98dB。
• 实现了高达150MHz输入频率的IF采样能力，同时保持SNR>76dB和SFDR>85dB。

🏷 关键词

📄 原文摘要

ADCs with emphasis on low power, and the ability to IF-sample to reduce receiver complexity. Further, the often-overlooked metric of small-signal linearity, quantified by SFDR for less-than-full-scale inputs is important, especially in the presence of large interferers. This 16b pipeline ADC achieves 78.7dB SNR, 78.6dB SNDR and 96dB SFDR at 125MS/s with a 30MHz input, while dissipating 385mW from a 1.8V supply. The ADC quantizes inputs up to 150MHz with an SNR >76dB and an SFDR >85dB, has a jitter of 65fs and accepts 2Vpp-diff inputs. Further, with dithering enabled the worst spur is <-98dB for inputs below -4dBFS at 100MHz IF. The ADC is fabricated in a 1P5M 0.18µm CMOS process. In pipeline ADCs, the front-end SHA and the first multiplying DAC (MDAC) are the dominant noise, distortion and power contributors. Eliminating the SHA

👥 作者与机构

Siddharth Devarajan, Larry Singer, Dan Kelly, Steven Decker,

Abhishek Kamath, Paul Wilkins Analog Devices, Wilmington, MA Today’s communication systems require high-performance low-cost