A 9b 14µW 0.06mm2 PPM ADC in 90nm Digital CMOS

📋 论文概要

该论文提出了一种基于脉冲位置调制(PPM)的ADC架构，利用CMOS工艺缩放带来的时间分辨率优势，通过将输入信号转换为时间间隔来克服电压分辨率退化问题。在90nm数字CMOS工艺中实现了9位分辨率、14µW功耗和0.06mm²小面积。

💡 主要创新点

• 首次提出基于PPM的ADC架构，利用时间域量化替代传统电压域量化，适应先进CMOS工艺的时间分辨率优势。
• 采用连续时间比较器和斜坡电压将输入信号转换为脉冲位置，实现低功耗小面积设计。

🏷 关键词

📄 原文摘要

University of Michigan, Ann Arbor, MI, National Semiconductor, Salem, NH As CMOS dimensions scale down, time-domain resolution of digital signals improves but the voltage resolution of analog signals degrades [1]. In this paper, we introduce an ADC architecture based on Pulse Position Modulation (PPM), which relies more on time resolution than on amplitude resolution. In PPM (Fig. 9.4.1(a)), a continuous-time comparator compares the input signal with a voltage ramp. The time interval between the ramp starting point, which is synchronous with the reference clock, and the instant the input signal crosses the ramp (i.e. [t1, t2, t3, ...] in Fig. 9.4.1(a)) is measured by a 2-step time-to-digital converter. Assuming the ramp slope is constant, we can calculate the input-signal amplitude from the measured time vector. Unlike a conventional ADC, the PPM ADC samples the input non-uniformly. An oversampling ratio of 8× or higher is required if a traditional linear recovery

👥 作者与机构

Shahrzad Naraghi1, Matthew Courcy2, Michael P. Flynn1, 1