A 1.2V 2MHz BW 0.084mm2 CT ∆Σ ADC with -97.7dBc THD and 80dB DR Using Low-latency DEM

📋 论文概要

该论文提出了一种1.2V供电、2MHz带宽的连续时间ΔΣ ADC，采用低延迟DEM技术解决传统CT ΔΣ ADC的时钟抖动敏感性和过量环路延迟问题，实现了-97.7dBc THD和80dB动态范围，面积仅0.084mm²。

💡 主要创新点

• 采用低延迟DEM技术，有效减少量化器和DEM的延迟，解决过量环路延迟问题。
• 使用NRZ多比特DAC，通过增加DAC电平数来降低时钟抖动敏感性，在保证信噪比的同时提升性能。

🏷 关键词

📄 原文摘要

Due to their inherent anti-aliasing properties and potential for low-power design, continuous-time (CT) ∆Σ ADCs are an indispensable component in wireless communication systems such as GSM/WCDMA, since a precise sampling network is not required. However, conventional CT ∆Σ ADCs suffer from 2 main problems: 1) high sensitivity to clock jitter, and 2) excess loop delay stemming from quantizer and DEM latency. To tackle the first problem, an NRZ multi-bit DAC can be used to trade achievable SNR with an increased number of DAC levels [1-3]. The NRZ nature dictates the addition of deliberate z-1 or z-1/2 terms in the loop to accommodate delay from the quantizer and DEM, which in turn requires a local feedback DAC around the quantizer to stabilize the loop. However, ISI-induced distortion remains prominent. A 1b SC DAC is used in [4] for low jitter sensitivity and elimination of DEM, at the expense of

👥 作者与机构

Sheng-Jui Huang, Yung-Yu Lin

MediaTek, Hsinchu, Taiwan