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本文提出一种12位50MS/s的全差分零交叉电路(ZCBC)流水线ADC,无需共模反馈(CMFB)。该设计通过用电流源和零交叉检测器替代传统运放,解决了CMOS工艺缩放中增益和输出摆幅下降的挑战。
As intrinsic device gain and power supply voltages decrease with CMOS technology scaling, it is becoming increasingly challenging for designers of conventional opamp-based switched-capacitor circuits to meet gain and output swing targets, and to ensure stability. Zero-crossing based circuits (ZCBC) are presented in [1-3] as an alternative architecture where each opamp is replaced with a current source and a zero-crossing detector. This changes the dynamics of the system while preserving the functionality. To further improve the robustness of ZCBC designs, we present a 50MS/s, 12b ZCBC pipelined ADC with fully differential signaling and automatic offset compensation. A simplified schematic and timing diagram of 2 adjacent fully differential ZCBC pipeline stages are shown in Fig. 9.3.1 and Fig. 9.3.2, respectively. During the sampling phase, the input voltage is sampled onto sampling capacitors C1±
Lane Brooks, Hae-Seung Lee
Massachusetts Institute of Technology, Cambridge, MA