A 1.7mW 11b 250MS/s 2× Interleaved Fully Dynamic Pipelined SAR ADC in 40nm Digital CMOS

📋 论文概要

本文提出了一种全动态、2倍交织的流水线SAR ADC，在40nm CMOS工艺下实现了1.7mW功耗、250MS/s采样率和9.5 ENOB，解决了高速高能效ADC的需求。

💡 主要创新点

• 采用全动态电路设计，消除了静态功耗，实现极低功耗。
• 通过2倍交织和流水线SAR架构，在保持高能效的同时将采样率提升至250MS/s。

🏷 关键词

📄 原文摘要

Renesas Electronics, Kawasaki, Japan 1 2 In recent years ADC research has resulted in impressive advances in power efficiency. SAR ADCs have reached energies per conversion step below 10fJ, but only at rather low sampling frequencies [1] or moderate resolution [2]. Wireless receivers for next-generation, higher-bandwidth standards such as LTEadvanced, however, will require much faster ADCs. We present a fully dynamic, two-times interleaved pipelined SAR ADC that achieves 10fJ/conversion-step with 9.5 ENOB at a sampling speed as high as 250MS/s. Figure 27.5.1 shows a block diagram of the ADC, consisting of a bootstrapped front-end sampling switch operating at the full clock frequency, two interleaved ADC channels and a multiplexer combining their outputs. The front-end sampling switch uses a 50% duty cycle and turns off first, eliminating potential timing mismatch between the two channels. Each channel consists of a 6b coarse

👥 作者与机构

Bob Verbruggen1, Masao Iriguchi2, Jan Craninckx1

imec, Leuven, Belgium