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该论文提出了一款14位3/6GHz电流舵射频DAC，采用0.18μm CMOS工艺，在2.9GHz输出频率下实现了66dB的ACLR，解决了高速DAC在高频信号纯度方面的动态误差问题。
The growth in communications coupled with the move towards multi-carrier, multi-band, multi-standard radio transmitters have helped drive high-speed digital-to-analog converter (DAC) technology for over a decade. The critical challenge for these DACs is realizing the highest possible signal purity at the DAC output. While DC linearity (from current source mismatch, for example) can be a factor, in most cases dynamic errors are the performance limiters. In [1] a 14b, 1.3GS/s DAC that uses a “quad-switch” architecture is presented. In that implementation, high-frequency distortion performance is improved using two pairs of differential switches instead of a single traditional pair. The two pairs are alternatively activated at each clock phase, creating a “transition event” even when there is no “bit change”. As result of this code-independent switching activity, the corresponding signal-dependent disturbance at the common-source node of the switches is reduced with clear benefits to high
Gil Engel, Shawn Kuo, Steve Rose
Analog Devices, Wilmington, MA