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该论文提出了一种低功耗单比特连续时间ΔΣ模数转换器，采用FIR DAC降低时钟抖动敏感度并放松环路滤波器线性度要求，通过模拟路径补偿FIR DAC引入的延迟，实现了3.6GS/s采样率、36MHz带宽、83dB动态范围，功耗仅15mW。
We propose design techniques that enable the realization of power-efficient single-bit CT-ΔΣ ADCs at multi-Gb/s speeds. An FIR DAC [1] is used to reduce sensitivity to clock jitter and relax loop filter linearity. A mostly analog path compensates the modulator for the delay introduced by the FIR DAC. The CTDSM samples at 3.6GS/s, has 83dB DR in 36MHz BW, and occupies 0.12mm2 in 90nm CMOS. Dissipating 15mW from a 1.2V supply, it thereby achieves an FoMSNDR of 72.8fJ/level, which is an improvement over the state of the art for converters with bandwidths greater than 20MHz. The number of quantizer levels is a key design choice affecting the ADC architecture. Many prior-art DSMs [2] use a 4b quantizer to achieve wide bandwidths. Alternatively, a 1b quantizer can be used, but the sampling rate should be increased to achieve the desired DR. A 1b quantizer operating at 3.6GS/s consumes less power than a 4b quantizer working at half the speed. Further, DEM
Pradeep Shettigar, Shanthi Pavan
Indian Institute of Technology, Madras, India