A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC Using Residue-Cancelling VCO-Based Quantizer

📋 论文概要

该论文提出了一种基于残差消除VCO量化器的连续时间ΔΣ模数转换器，解决了VCO非线性导致的失真问题，实现了16mW功耗下78dB SNDR和10MHz带宽。

💡 主要创新点

• 采用残差消除技术补偿VCO的非线性电压-频率转换特性，显著提升线性度。
• 将VCO量化器嵌入ΔΣ环路中，利用噪声整形和残差消除实现高精度。
• 在低功耗下实现高SNDR和宽带宽，适合高速低功耗应用。

🏷 关键词

📄 原文摘要

conversion presents an attractive means of implementing high-bandwidth oversampling ADCs [1,2]. They exhibit inherent noise-shaping properties and can operate at low supply voltages and high sampling rates [1-3]. However, usage of VCO-based ADCs has been limited due to their nonlinear voltage-to-frequency (V-to-F) transfer characteristic, which severely degrades their distortion performance. Digital calibration is used to combat nonlinearity in an open-loop VCO-based ADC, but 1storder noise-shaping mandates high OSRs, thus increasing power dissipation in digital circuits, even in a nanometer-scale CMOS process [1]. In [2], nonlinearity is suppressed by embedding the VCO in a ΔΣ loop. While this technique works in principle, the need for large loop gain at high frequencies makes it very difficult to achieve high SNDR. For instance, the suppression

👥 作者与机构

Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly,

Mrunmay Talegaonkar, Pavan Kumar Hanumolu Oregon State University, Corvallis, OR Voltage-controlled oscillator (VCO) based analog-to-digital