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本文提出一种在45nm CMOS工艺中时钟频率为6GHz的1比特三阶连续时间ΔΣ调制器，通过最小化过量环路延迟（ELD）的电路技术和补偿方案，实现了20mW功耗下61dB SNDR、60MHz带宽的性能，解决了高速调制器中ELD导致的稳定性问题。
ADCs in deep-submicron processes [1-4]. The maximum sampling rate is set by Excess Loop Delay (ELD) considerations. ELD comprises the comparator latency, feedback DAC delay (DEM delay etc.) and any additional delay due to parasitics. For a wideband 1b modulator clocking at high speeds (multi-GHz), the key challenge is modulator stability due to large ELD set by comparator speed limitations and integrator parasitic poles. This paper describes circuit techniques to minimize ELD and a compensation scheme that ensures modulator stability given a 1clock-period ELD. These techniques have enabled the design of a 3rd-order 1b modulator clocked at 6GHz in 45nm CMOS. Traditional techniques for ELD compensation use a DAC in a fast feedback loop around the comparator such that the comparator’s decision is fed back in time
Venkatesh Srinivasan, Victoria Wang, Patrick Satarzadeh,
Baher Haroun, Marco Corsi Texas Instruments, Dallas, TX Continuous-Time ΔΣ Modulators are a popular architecture choice for