A 28nm 6GHz 2b Continuous-Time ∆Σ ADC with -101dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction

📋 论文概要

这篇论文提出了一款采用28nm CMOS工艺的6GHz采样率、2比特连续时间ΔΣ ADC。通过数字DAC误差校正技术，实现了-101dBc的总谐波失真（THD）和120MHz带宽，解决了宽带高线性度ADC的设计挑战。

💡 主要创新点

• 采用2比特连续时间ΔΣ调制器架构，在保持高线性度的同时实现宽带信号处理。
• 提出数字DAC误差校正技术，有效补偿DAC非线性，显著降低失真。
• 实现了6GHz采样率与120MHz带宽的均衡，兼顾高速与高精度。

🏷 关键词

📄 原文摘要

continuous-time ∆Σ modulators with a (theoretically) linear 1b DAC, have demonstrated better than -100dBc THD in a bandwidth range from tens of kHz for audio to tens of MHz for broadband AM/FM radio [1]. To achieve both a large bandwidth and high dynamic range with a 1b ∆Σ modulator, a high OSR and multiGHz-rate sampling frequency are required. But there is a limit to the maximum sampling frequency of a ∆Σ modulator, being a negative feedback system, in order to maintain loop stability and sufficiently low metastability, for a given technology node. To date, the maximum achievable bandwidth of a high-resolution 1b ∆Σ modulator is limited to a few tens of MHz. To achieve a bandwidth exceeding 100MHz with a single-loop ∆Σ modulator, multi-bit quantization is essential [3-5]. When employing multi-bit

👥 作者与机构

Muhammed Bolatkale1, Robert Rutten1, Hans Brekelmans1, Shagun Bajoria1,

Yihan Gao1, Bernard Burdiek2, Lucien Breems1 NXP Semiconductors, Eindhoven, The Netherlands NXP Semiconductors, Hamburg, Germany 1 2 Ultra-highly linear ADCs, based on