A 47.0Tb/s/mm 112Gb/s/pin PAM4 Single-Ended Transceiver Featuring 4-Aggressor Crosstalk Cancellation and Supply-Noise Tolerance for Short-Reach Memory Interfaces

📋 论文概要

该论文提出一种五通道112Gb/s/pin PAM4单端收发器，采用28nm CMOS工艺，用于高密度短距离存储器接口。通过低功耗三重均衡、4-aggressor形状拟合串扰消除和电源噪声容忍时钟分布网络，实现了47.0Tb/s/mm边缘密度和0.52pJ/b能效。

💡 主要创新点

• 采用4-aggressor形状拟合串扰消除技术，有效抑制多路串扰。
• 提出低功耗三重均衡技术，在保证信号完整性的同时降低功耗。
• 设计电源噪声容忍时钟分布网络，提高系统对电源噪声的鲁棒性。

🏷 关键词

📄 原文摘要

Interdisciplinary Research Center for Future Intelligent Chips (Chip-X), Suzhou, China 1 3 Abstract This paper presents a five-lane 112Gb/s/pin PAM4 single-ended transceiver in 28nm CMOS for high-density short-reach memory interfaces. Low-power triple-equalization, 4-aggressor shape-fitting crosstalk cancellation and supply-noise-tolerant clock distribution networks are involved to improve the signal integrity. The design demonstrates robust performance against severe crosstalk and supply noise, achieving an energy efficiency of 0.52pJ/b and an edge density of 47.0Tb/s/mm. The rapid advancement of high-performance computing and AI promotes the evolutions of short-reach memory interfaces (e.g. HBM), die-to-die and chiplet links (e.g. UCIe); these interfaces utilize single-ended (SE) data transmissions for high-bandwidth I/O density. However, SE signaling is vulnerable to interference and noise: e.g. crosstalk (XT) and supply

👥 作者与机构

Qian Liu1, Yiheng Hui1, Yuanlin Nong1, He Ma1, Yiwei Xu1, Hao Hu1, Jinpeng Zhu1, Quan Wang2, Lei Wang2, Li Du1,3, Yuan Du1,3

Nanjing University, Nanjing, China, 2T-Head (Shanghai) Semiconductor Co., Ltd., Shanghai, China