A 4042-PPI 10b 240Hz Digital-PWM CMOS Backplane for Micro-LED-on-Silicon Displays with a Shared, Unified Memory-in-Pixel Architecture

📋 论文概要

本文提出了一种用于微发光二极管硅基显示的数字PWM CMOS背板，采用共享统一的内存-像素结构，实现了4042 PPI的高分辨率和10位240Hz的刷新率。通过统一D触发器链和分层时分PWM技术，解决了像素内寄存器、计数器和比较器集成的问题，并提高了面积效率。

💡 主要创新点

• 提出统一D触发器链(UDC)，将像素内寄存器、计数器和比较器合并为一个可重构单元，节省面积和功耗。
• 采用分层时分PWM(HTD-PWM)与 shuffled rolling-shutter(SRS)技术，将LSB引擎在1×6像素簇间时分复用，实现高效PWM驱动。

🏷 关键词

📄 原文摘要

Abstract This paper presents a 10b 240Hz digital-PWM CMOS backplane for μLED-on-Silicon with a shared, unified memory-in-pixel structure. A unified D-FF chain (UDC) merges the in-pixel register, counter, and comparator into one reconfigurable unit. Hierarchical time-divided PWM (HTD-PWM) with shuffled rolling-shutter (SRS) time-multiplexes an LSB engine across 1×6 pixel clusters. Fabricated in 28nm CMOS, the 120×120 backplane achieves 4042PPI and an 88% active-area, with DNL/INL of 0.9/7.1LSBs. Micro-light-emitting diode (μLED) is a promising technology for next-generation AR/VR head-mounted displays (HMDs) [1–4]. However, achieving high-quality, cost-effective μLED-on-silicon (μLEDoS) displays requires a CMOS backplane that meets several key requirements (Fig. 24.2.1, top). First, constant-current driving is essential for color stability, as the μLED emission wavelength is current-density dependent [5,6]. Second, high pixelsper-inch (PPI) demands an extremely compact pixel circuit. Th

👥 作者与机构

Kihyun Kim, Jun-Gi Lee, Hyun-Sik Kim

KAIST, Daejeon, Korea