A 0.87pJ/b 17Gb/s/pin Parallel Receiver with a Local DQS Recovery for a Supply-Noise-Tolerant DQS Distribution in High-Performance NAND Flash Interfaces

📋 论文概要

本文提出一种0.87pJ/b、17Gb/s/pin的并行接收器，采用本地DQS恢复和双DQS树结构，以降低时钟功耗并抑制电源噪声引起的抖动（PSIJ）。该设计通过时间复用CML和反相器树（1/8:7/8）实现对CML树的隐藏锁定，进而从低功耗反相器树生成PSIJ滤波的DQS，在40nm CMOS工艺下实现100mVpp电源噪声下BER<10^-12，并减少70%时钟功耗。

💡 主要创新点

• 提出本地DQS恢复技术，通过时间复用CML和反相器树，实现隐藏锁定和低功耗PSIJ滤波。

📄 原文摘要

Abstract This work presents a 0.87pJ/b, 17Gb/s/pin parallel receiver with local DQS recovery and a dual-DQS tree for reduced clock power and mitigated power supply-induced jitter (PSIJ). The local DQS recovery time-multiplexes a CML and an inverter tree (1/8:7/8), enabling a hidden lock to the CML tree and subsequently generating a PSIJ-filtered DQS from the inverter tree with low power consumption. Fabricated in 40nm CMOS, it achieves <10-12 BER under 100mVPP supply noise, while reducing clocking power by 70%. The rapid advancement of AI and large-scale data processing has increased the demand for higher data rates in memory interfaces. While modern DRAM supports multi-Gb/s throughput, conventional NAND interfaces remain limited by their DQ-to-DQS delaymatched architecture. As shown in Fig. 37.8.1, this structure provides strong immunity to power supply-induced jitter (PSIJ), but it precludes the use of advanced equalization

👥 作者与机构

Byeong-Chan Kim1, Kyongsu Lee1, Dongjun Park1, Jung-June Park2, Chiweon Yoon2, Jae-Yoon Sim1, Seon-Kyoo Lee1

Pohang University of Science and Technology, Pohang, Korea, 2Samsung Electronics, Hwaseong, Korea