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本文提出了一种全集成压电能量收集接口,采用开关电容结构复用压电电容和整流电容作为飞电容,并使用片上电容作为直流电容,消除了寄生电容损耗。该设计实现了5.63倍的最大输出功率提升和0.09 mm²/nF的归一化片上电容面积。
Abstract This paper presents a fully integrated PEH interface that enhances output power while minimizing on-chip capacitor area. The proposed design employs a SC structure that reuses both the piezoelectric capacitor and the rectifier capacitor as flying capacitors. Meanwhile, on-chip capacitors serve as DC capacitors, thereby eliminating parasitic-capacitance losses. As a result, the interface achieves a maximum output power improvement of 5.63× and a normalized on-chip capacitor area of 0.09 mm2/nF. Piezoelectric energy harvesting (PEH) has emerged as a promising solution for scavenging vibration energy to power miniaturized Internet-of-Things (IoT) devices. A fundamental PEH interface consists of two parts (Fig. 16.3.1 top left): a Bias-Flip (BF) AC-DC stage that rapidly reverses the piezoelectric transducer (PT) voltage (VPT) when the PT current (IP) crosses zero, minimizing energy loss on the piezoelectric capacitor (CP), and a DC-DC converter
Xiaonan Wu1, Jinyi Yuan1, Minghao Shang1, Baochuang Wang1, Sijun Du2, Lin Cheng1
University of Science and Technology of China, Hefei, China, 2TU Delft, Delft, The Netherlands