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本文提出了一种在2nm纳米片CMOS技术中实现的单轨、逻辑位单元2端口SRAM，采用2R×1C配置和双位线设计以实现高面积密度和动态功耗优化。该SRAM可在0.35V至1.2V电压下可靠工作，读访问时间达102ps，支持4GHz处理器，适用于移动和边缘AI应用中的浅深度缓存。
Abstract This work presents a single-rail, 21.04Mb/mm2 logic-bitcell 2-port SRAM in a 2nm nanosheet technology for CPU, GPU and NPU caches. The implemented xBIT cell in a 2R×1C configuration uses dual BL for balanced NMOS/PMOS devices to form a rectangular array and maximize area density. Optimized for dynamic power, it operates reliably from 0.35 - 1.2V, achieving an industry-leading 102ps read-access time to support 4GHz processor and making it ideal for shallow-depth caches. SRAM is critical in modern compute systems for optimizing system-level power, performance, and area (PPA). For CPUs, GPUs and NPUs it provides low-latency memory access in the form of caches, register files or scratchpads; thereby, accelerating data access and storing weights to support high-speed processing. In addition, these systems use voltage-frequency scaling to improve efficiency, requiring SRAM to function across a wide
Manish Trivedi1, Sandipan Sinha1, Ramesh Halli1, Girishankar Gurumurthy1, Jaswinder Singh1, Chun-Yuan Cheng2, Linchien Chen2, Jeff Lin2, Hugh Mair3
MediaTek, Bengaluru, India, 2MediaTek, Hsinchu, Taiwan, 3MediaTek, Austin, TX