⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一款28nm工艺下的位并行数字计算内存(CIM)宏，采用基于转移计数线(TCL)的无损压缩器进行比特列加法。通过符号位嵌入的总线TCL支持有符号2的补码MAC操作，并利用阶段式使能电路减少加法器不必要的翻转，提升能效42%。该CIM宏在INT8和BF16精度下分别实现了106.85TOPS/W和77.68TFLOPS/W的能效。
Abstract This paper proposes a bit-parallel digital CIM macro featuring a lossless compressor based on transition-counting-lines (TCLs) for bit-column addition. The bus TCL incorporates signbit extension to support signed 2’s-complement MAC operations with minimal area overhead. A stage-wise enabling circuit prevents unnecessary toggling of adders, improving energy efficiency by 42%. Leveraging these techniques, the proposed CIM macro, which is fabricated in 28nm CMOS, achieves 106.85TOPS/W for INT8 operations and 77.68TFLOPS/W for BF16 operations. SRAM CIM macros improve energy efficiency for edge-AI devices. In contrast to “bit-serial” CIM macros [1], “bit-parallel” CIM directly matches the data format of computing systems, eliminating the parallel-to-serial conversion and specialized weight mapping strategies [2,3]. It can also reduce the MSB toggle rate [4], thereby lowering power consumption. Current
Lichen Feng, Yunlong Liu, Lin Wu, Dong Li, Zhangming Zhu
Xidian University, Xi’an, China