A 12nm 4Mb 104.56-to-137.75TFLOPS/W Charge-Trap Transistor-Based Computing-in-Memory Macro Using Analog-Predict-DigitalCompute for AI Edge Devices

📋 论文概要

本文提出了一款基于电荷陷阱晶体管(CTT)的4Mb非易失性计算存储一体(nvCIM)宏，采用12nm CMOS工艺制造。该宏支持INT/FP4 MAC操作，并引入模拟预测数字计算(APDC)方案以降低功耗，实现了137.75TFLOPS/W的能效和超过40倍的密度FoM（存储密度×计算密度）提升，解决了传统nvCIM宏存储密度低、不必要的MAC操作和浮点计算硬件成本高的问题。

💡 主要创新点

• 首次采用电荷陷阱晶体管(CTT)构建4Mb nvCIM宏，在12nm工艺下实现高密度非易失性存储与计算。
• 提出模拟预测数字计算(APDC)方案，通过预测跳过不必要的MAC操作，显著降低功耗。
• 支持INT/FP4混合精度MAC操作，在保持精度的同时大幅提升能效至137.75TFLOPS/W。

🏷 关键词

📄 原文摘要

2University of Chinese Academy of Sciences, Beijing, China Columbia University, New York, NY *Equally Credited Authors (ECAs) 1 3 Abstract Previous non-volatile CIM (nvCIM) macros suffer from low storage density, unnecessary multiply-and-accumulate (MAC) operations, and large hardware cost for floating point computations. A 4Mb CTT nvCIM macro, fabricated in 12nm CMOS, supports INT/FP4 MAC operations with the analog-predict-digital-compute scheme for power saving, achieving an energy-efficiency of 137.75TFLOPS/W and >40 times improved density FoM (storage density×computing density). Recent AI workloads increasingly consist of low-computation-intensity operations, where memory access dominates power and latency [1]. Non-volatile computing-in-memory

👥 作者与机构

Junzhe Shen*1,2, Zhidao Zhou*1,2, Wenfeng Zha1,2, Zhi Li1,2, Weizeng Li1,2, Bohan Wang1,2, Junyu Zhu1,2, Hanghang Gao1,2, Zhongze Han1,2, Yiman Wang1,2,

Linfang Wang3, Hongyang Hu1,2, Qing Luo1,2, Chunmeng Dou1,2, Ming Liu1 Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China,