ReFIND: A Resolution-Reconfigurable Bio-Signal Classification SoC Enabling >10× Savings in AFE Power per Channel

📋 论文概要

该论文提出ReFIND，一款集成16个分辨率可重构AFE、特征提取器和分类器的生物信号分类SoC。通过VCO ADC的积分时间缩放实现功耗与分辨率的动态权衡，端到端验证表明相比固定阵列可节省超过14倍AFE每通道功耗，为生物信号分类器提供运行时功耗性能优化。

💡 主要创新点

• 提出分辨率可重构的VCO ADC架构，通过缩放积分时间在13位至10位分辨率下实现1.77μW至0.12μW/通道的功耗动态调节。
• 集成16通道AFE、特征提取器和分类器的完整SoC，支持运行时分辨率缩放，实现超过10倍的AFE每通道功耗节省。
• 端到端验证显示比固定阵列节省14倍功耗，比传统通道选择方法多3倍，显著提升能效。

🏷 关键词

📄 原文摘要

Abstract This work presents ReFIND, an SoC integrating together 16 resolution-reconfigurable AFEs, a feature extractor, and a classifier. The VCO ADC architecture trades power for resolution by scaling the integration time, from 13 to 10b at 1.77 to 0.12μW/channel. End-to-end validation shows up to 14× power saving over a fixed array, 3× more than channel selection. ReFIND enables runtime resolution scaling, opening up power-performance optimization in bio-signal classifiers. Bio-signal recording front ends, which digitize microvolt-level signals from the body, are central to both wearable and implantable neural interfaces. Signals from these front ends are filtered, featurized, and decoded through machine-learning algorithms to the parameter of interest. As decoding tasks become increasingly complex, these front ends must support high channel counts under strict power budgets, constrained by battery capacity and tissue

👥 作者与机构

Aviral Pandey1, I-Ting Lin1, Dhruv Vaish1, Ashwin Rammohan1, Savit Bhat1, Jade Pinkenburg1, Rikky Muller1,2

University of California, Berkeley, CA, 2Weill Neurohub, Berkeley, CA