A Vertical-Cell-Transistor-Based 4F2 DRAM with Cell-on-Peripheral Architecture Using Wafer-to-Wafer Hybrid Copper Bonding

📋 论文概要

该论文提出了一款基于垂直沟道晶体管的4F2 DRAM，采用单元外设（COP）架构，并应用晶圆对晶圆混合铜键合技术。相比相同设计规则的传统方案，其每晶圆芯片总数提升超过20%，并在10纳米级DRAM工艺中成功实现了16Gb SDRAM的读写操作。

💡 主要创新点

• 提出垂直沟道晶体管4F2单元结构，实现更高密度存储。
• 采用晶圆对晶圆混合铜键合技术实现单元外设（COP）架构，使每晶圆芯片数量增加超过20%。

🏷 关键词

📄 原文摘要

Sang-Hoon Jung, Seunghan Woo, Donggeon Kim, Jonghyuk Kim, In Jung, Junsoo Kim, Jae-Joon Song, InCheol Nam, Young-Hun Seo, Sungsoo Yim, Jemin Park, Changsik Yoo, SangJoon Hwang Samsung Electronics, Hwaseong, Korea Abstract The paper presents a 16Gb SDRAM with a vertical-channel-transistor-based 4F2 cell and cell-on-peripheral (COP) architecture. Wafer-to-wafer hybrid copper bonding is applied to COP, which increases the total die count per wafer by more than 20% with the same design rules. Fabricated in a 10nm-class DRAM process, the test chip performs read and write operations successfully, opening the possibility for further DRAM-technology scaling. The scalability of dynamic random-access memory (DRAM), which integrates capacitors and transistors within a 2-dimensional environment, is facing physical limitations. On the other hand, industry trends consistently demand higher density and bandwidth at a reduced

👥 作者与机构

Hyunchul Yoon, Youngseok Park, Tae Jin Park, Suk Lae Kim, Seungjae Jung, Daesun Kim, Kyunghwan Kim, Yongjun Kim, KyuChang Kang, Bokyeon Won,