A Binary-Weighted Switched-Capacitor Gate Driver IC for Overcoming Trade-offs Between Driving Loss and Delay Time with Gate-Current Feedback Achieving 85% Driving Loss Reduction

📋 论文概要

本文提出了一种二进制加权开关电容栅极驱动IC，通过四级二进制加权飞电容实现九级栅极电压分段，并采用基于栅极电流反馈的自适应状态间隔时间控制，有效解决了驱动损耗与延迟时间之间的权衡问题。实验结果表明，该设计在相同驱动损耗下将开关时间降低19%，在相同开关时间下将驱动损耗降低9%。

💡 主要创新点

• 采用四个二进制加权飞电容实现九级栅极电压分段，增强了电荷供应能力。
• 提出基于栅极电流反馈的自适应状态间隔时间控制，动态优化开关时间与驱动损耗的权衡。

🏷 关键词

📄 原文摘要

Abstract A binary-weighted switched-capacitor gate driver IC achieving up to 85% reduction in driving loss (Edrv) is presented. Four binary-weighted flying capacitors enable nine-level gate-voltage segmentation, enhancing charge supply capability. Adaptive state interval time control based on gate-current feedback mitigates the trade-off between the switching time of the gatevoltage (tsw) and Edrv, reducing tsw by 19% at equal Edrv, and reducing Edrv by 9% at equal tsw. In recent years, the importance of converters employing high-voltage high-current power devices have grown in response to the rising demand from data center UPSs and onboard chargers for electric vehicles. To maximize converter power density, it is essential to integrate the gate driver IC and minimize the size of the power supply. However, these highpower devices typically exhibit large input capacitance$Ciss$and require a large gate voltage

👥 作者与机构

Kohei Horii, Koutaro Miyazaki, Shusuke Kawai, Hiroaki Ishihara

Toshiba, Kawasaki, Japan