A 55nm Intelligent Vision SoC Achieving 346TOPS/W System Efficiency via Fully Analog Sensing-to-Inference Pipeline

📋 论文概要

本文提出了一种全模拟智能视觉SoC，通过PWM成像器、RRAM存内计算和线性恢复模拟存储器实现了从传感到多层推理的连续模拟数据通路，消除了传感器-处理器和层间A/D转换。在55nm CMOS工艺下，芯片实现了346 TOPS/W的系统级能效，适用于边缘AI视觉任务。

💡 主要创新点

• 提出完全模拟的传感到推理流水线，消除了传感器-处理器和层间A/D转换，实现端到端视觉处理。

📄 原文摘要

presents a fully analog intelligent vision SoC that eliminates both sensorprocessor and inter-layer A/D conversions for end-to-end vision. A continuous analog datapath from sensing to multi-layer inference is enabled by a PWM imager, an RRAM- based CIM, and a linearity-recovery analog memory. Fabricated in 55nm CMOS, the chip achieves 11pJ/(pixel·frame) sensing efficiency, 8,791 TOPS/W MAC efficiency, and 346 TOPS/W system-level efficiency across diverse vision tasks. Artificial intelligence (AI)-enabled vision systems are rapidly expanding at the edge, requiring versatile support for tasks ranging from feature extraction and region-of-interest (RoI) detection to object recognition. Imagers with stacked digital processors and memory [1,2]

👥 作者与机构

Zhengke Yang1, Haofeng Yu1, Xiao Liu1, Zhen Kong1, Humiao Li1, Liang Ran2, Zhichao Lyu3, Xinhe Feng2, Liang Zhao3, Yida Li1, Jiamin Li1, Feichi Zhou1, Longyang Lin1

Southern University of Science and Technology, Shenzhen, China, 2Beijing Pixelcore Technology, Beijing, China, 3Hefei Reliance Memory, Hefei, China 1 Abstract This work