A 2nm All-Digital 14.4Gb/s/pin LPDDR6 PHY with Quarter-Rate Clocking Architecture and Multi-Level FIFO-Based Speculative DFE

📋 论文概要

本文提出了一款基于2nm工艺的全数字LPDDR6 PHY，通过四相时钟架构与多级FIFO推测式DFE，实现了14.4Gb/s/pin的高速数据传输，同时降低了抖动敏感度和时序约束。采用时钟门控的高效模式显著降低了功耗。

💡 主要创新点

• 提出四相时钟架构配合正交误差校正（QEC），降低抖动敏感度，提升时钟质量。
• 采用多级FIFO为基础的推测式判决反馈均衡器（DFE），放宽标准单元实现的时序约束。
• 引入时钟门控的高效模式，大幅降低功耗，并通过可重构串行器支持1:6和1:8 DFI，保证总线效率与向后兼容。

🏷 关键词

📄 原文摘要

LPDDR6 PHY that achieves 14.4Gb/s/pin, increasing bandwidth while optimizing power. Key innovations include quadrature clocking, with QEC, to reduce jitter sensitivity, and a multi-level FIFO-based speculative DFE to relax timing constraints in standard-cell implementation. An efficiency mode, employing clock gating, dramatically reduces power. A reconfigurable serializer supports both 1:6 and 1:8 DFIs, ensuring high bus efficiency and backward compatibility. Bandwidth demands of low-power double-data-rate (LPDDR) interfaces continues to grow to support AI, augmented reality (AR), and high-resolution multimedia workloads [1-3]. To meet demand, the PHY’s internal clock frequency is aggressively scaled; resulting, in

👥 作者与机构

Yoonjae Choi, Daero Kim, Myunggon Kim, Sangmin Lee, Hansol Kang, Gwangwon Lee, Yoonhyung Kim, Sungsik Kang, Hyun Cho, Boyoung Kang,

Kyoungwon Lee, Jaegeun Song, Jinho Choi, Shinyoung Yi, Billy Koo, Kwanyeob Chae, Hyo-Gyuem Rhew Samsung Electronics, Yongin, Korea Abstract This paper presents a 2nm all-digital