A 72Gb/s/pin Single-Ended Simultaneous Bi-Directional Transceiver with C-Peaking Leakage Cancellation and Dual-Loop Hybrid Impedance Calibration for Chiplet Interfaces

📋 论文概要

提出了一种72Gb/s/pin单端同时双向收发器，采用电容峰值泄漏消除技术抑制主驱动器和混合驱动器失配引起的高频泄漏63%，并利用双环混合阻抗校准将PVT变化下的混合电路系数误差降低92%。该收发器在28nm CMOS工艺下实现了72Gb/s数据率、0.45UI和243mV眼图开度以及1.5pJ/b能效。

💡 主要创新点

• 电容峰值泄漏消除（CPLC）技术，有效抑制单端同时双向链路中因驱动失配造成的高频泄漏，泄漏抑制达63%。
• 双环混合阻抗校准技术，显著降低PVT变化下混合电路的系数误差，误差降低92%。

🏷 关键词

📄 原文摘要

Abstract This paper presents a 72Gb/s/pin single-ended simultaneously bi-directional (SBD) TRX in 28nm CMOS. Capacitive peaking leakage cancellation (CPLC) suppresses the high-frequency leakage due to the main and hybrid driver mismatch in SBD links by 63%. Dual-loop hybrid impedance calibration reduces the coefficient errors of the hybrid circuits under PVT variations by 92%. The TRX achieves a 72Gb/s data rate with an eye-opening of 0.45UI and 243mV and an energy efficiency of 1.5pJ/b. The explosive growth of artificial intelligence has accelerated the development of highperformance computing and high-bandwidth interconnects. Single-ended parallel links, like chiplet interfaces, are favored for their high bandwidth density and low bit-error rate (BER) [1-5]. Simultaneous bi-directional (SBD) links have shown potential to double the system throughput [6-7]. However, the design of high-speed bi-directional links is challenging. The

👥 作者与机构

Xuxu Cheng, Hongzhi Wu, Zhenghao Li, Weitao Wu, Xiongshi Luo, Yangyi Zhang, Quan Pan

Southern University of Science and Technology, Shenzhen, China