A 14Gb/s/pin 0.163pJ/b DQ Receiver for HBM with Baud-Rate Phase Tracking Loop Supporting Background Offset Calibration

📋 论文概要

本文提出了一种用于HBM的紧凑型14Gb/s/pin DQ接收器，采用波特率相位跟踪环路和背景校准的时间窗口相位检测器，在实时数据中连续跟踪采样相位和检测器偏移，消除了重新训练的需求。28nm原型实现了0.163pJ/b的能效和0.00547mm²的面积，在<10⁻¹²误码率下具有0.295UI的采样裕度。

💡 主要创新点

• 采用上升/下降沿触发决策逻辑，将相位误差与检测器偏移解耦，使采样时钟锁定点固定，无需重新训练。
• 提出背景校准的时间窗口相位检测器，在实时数据中连续跟踪相位和偏移，支持背景偏移校准。

🏷 关键词

📄 原文摘要

Abstract This paper presents a compact 14Gb/s/pin HBM DQ receiver that continuously tracks sampling phase and detector offset in live data, using a baud-rate phase tracking loop with a background-calibrated time-window phase detector. Rise/fall edge-triggered decision logic decouples phase error from detector offset, keeping the sampling-clock lock point of the DCDL fixed under drift and thereby eliminating the need for retraining. A 28nm prototype achieves 0.163pJ/b energy efficiency in 0.00547mm2 at <10-12 BER with a 0.295UI sampling margin. High-frequency jitter tolerance reaches 0.188UI at 14Gb/s. The shift in high-performance computing and memory systems toward multi-chip module packaging, short-reach die-to-die links, and standardized chiplet interfaces is driving requirements for increased bandwidth and I/O density at a low energy per bit [1-6]. Unlike long-reach serial I/Os, high-density memory interfaces typically avoid clock and data

👥 作者与机构

Jeonghyeon Lee1, Ho-Joon Shin1, Han-Gon Ko2, Kwanseo Park1

Yonsei University, Seoul, Korea, 2ONEsemiconductor, Gyeonggi, Korea