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ISSCC 2026Session 15 · DRAM, SRAM, AND NON-VOLATILE MEMORIESMemory

A 2Tb 4b/Cell 6-Plane 3D-Flash Memory with 37.6Gb/mm2 Bit Density and >85MB/s Write Throughput

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📋 论文概要

该论文提出了一款2Tb容量、4b/cell的6平面3D闪存,实现了37.6Gb/mm2的位密度和超过85MB/s的写吞吐量。通过优化架构和工艺,解决了高密度存储与写入性能之间的平衡问题。

💡 主要创新点

核心指标
37.6Gb/mm2 位密度, >85MB/s 写吞吐量
重要性
发表年份
ISSCC 2026

🏷 关键词

3D闪存4b/cell高密度存储写吞吐量6平面架构

📄 原文摘要

Kazuki Yamauchi2, Indra K V1, Masahiro Kano2, Sirisha Bhamidipati1, Sneha Bhatia1, Seema Malhotra1, Naoki Ojima2, Ella Wu3, Zhiyong Yang3, Frank W. Tsai3, Mathias Bayle2, Naoyuki Minami2, Yasuyuki Fujihara2, Kei Kitamura2, Tomofumi Kitani2, Takuyo Kodama4, Takaya Handa4, Naoaki Kanagawa4, Yuki Ishizaki4, Susumu Fujimura4, Yoshinao Suzuki4, Mario Sako4, Yumi Higashi4, Yoshihisa Watanabe4, Toshiyuki Kouchi4, Aravinth V1, Chin-Yi Chen3, Xiang Yang3, Guirong Liang3, Jenny Wang3 Sandisk, Bengaluru, India, 2Sandisk, Yokohama, Japan, 3Sandisk, Milpitas, CA, 4KIOXIA, Yokohama, Japan 1 Abstract A 332-WL-layer stacked 2Tb 4b/Cell 6-plane 3D Flash memory achieves an areal density of 37.6Gb/mm2. An 8kB-physical and 16kB-logical page architecture realizes a <65µs read latency and a >85MB/s program throughput. Write throughput is enhanced by 4.2% through voltage-level sensing based on SEN2–LBUS coupling, and an additional 8% by reduced

👥 作者与机构

Jayanth M. Thimmaiah1, Ryuji Yamashita2, In-Soo Yoon3, Jason Li3, Cynthia Hsu3, Takuya Ariki2, Naoki Ookuma2, Yosuke Kato2, Koichiro Hayashi2,

分类:Memory · 年份:ISSCC 2026