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本文提出了一款在10纳米级工艺上实现的12.8Gb/s/pin LPDDR6 SDRAM，采用12-DQ/子通道宽NRZ信令和两个子通道架构，相比LPDDR5x实现了33.3%的带宽提升和21.0%的能效改善。同时引入每行激活（Per-Row Activation）技术增强可靠性。
JongMoon Choi, Sung-Woo Yoon, Sang Yun Kim, Dongkeon Lee, Minsoo Jang, Daehyun Kwon, Sangyong Lee, Jinguk Kim, Jonghyuk Kim, In Jung, Taeha Song, Chang Won Kim, Seung Ho Baek, Jinyong Choi, Young-Hun Seo, Won Ho Choi, Changsik Yoo, SangJoon Hwang Samsung Electronics, Hwaseong, Korea *Equally Credited Authors (ECAs) Abstract This paper presents a 12.8Gb/s/pin LPDDR6 SDRAM implemented in a 10-nm class process. It shows 33.3% higher bandwidth and 21.0% better energy efficiency than LPDDR5x by using wide NRZ signaling (12 DQ/sub-channel with two sub-channels) and optimum allocation of two supply rails (1.0 and 0.875V) across functional blocks. The dynamic and static efficiency modes provide better energy efficiency and higher capacity, respectively by dynamically or statically turning off the I/O circuitry of a sub-channel. The demand for high-bandwidth low-power DRAM is accelerating for various applications,
Kiheung Kim*, Hong-Joo Song*, Youngdo Um, Jinhun Jang, Seungjun Lee, Hoseok Seol, Hye-Jung Kwon, Ji-Hwan Seol, Hoon Shin, Jaehyung Lee,