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ISSCC 2026Session 30 · COMPUTE-IN-MEMORYAI / ML

A 28nm 127.54TFLOPS/W MXFP6 and 117.42TFLOPS/W MXFP8 Compute-in-Memory Macro with Adaptive-Preserved-Bit-Width and Serial-Dual-Bit-Sliding Schemes

📄 原文摘要

China, 3Xiaomi, Beijing, China, 4Peking University, Beijing, China 1 Abstract Conventional FP-CIMs suffer from fixed preserved bit-width (PBW), limiting their adaptability and efficiency. This work proposes the first MXFP-CIM macro enabling wide-range adaptive PBW, featuring: (1) A serial dual-bit-sliding scheme; (2) A harmless data mapping scheme with a hierarchical hidden-bit decoder; (3) An adjustable-PBW MXFP-MAC circuit via twinstage allocation. The 28nm MXFP-CIM macro achieves a peak energy efficiency of 127.54TFLOPS/W in the MXFP6/6 mode. With the rapid advancement of artificial intelligence (AI), neural network model sizes have grown exponentially, placing increasing demands on computational bandwidth, memory

👥 作者与机构

Xing Wang1,2, Yucheng Du1, Tianhui Jiao1, Defa Wu1, Xi Chen1, Miaoyu Tang1, Yi Yang1, Zhichao Liu1, An Guo1, Gaoming Fu3, Peng Li3, Jun Dong3, Bo Liu1,

Xinning Liu1, Weiwei Shan1, Hao Cai1, Guangyu Sun4, Lin Tong3, Jun Yang1,2, Xin Si1 Southeast University, Nanjing, China, 2National Center of Technology Innovation for EDA, Nanjing,

分类:AI / ML · 年份:ISSCC 2026