⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出一种16Gb/s/pin单端NRZ收发器，采用分布式双环补偿（DDLC）抑制VDDQ纹波，并集成动态占空比校准（DDCC）提升时钟鲁棒性。该设计将去耦电容减少91.4%，眼图水平/垂直裕度分别提升61%和36%，适用于高密度存储器接口。
*Equally Credited Authors (ECAs) 1 Abstract A 16Gb/s/pin 0.51pJ/b single-ended NRZ transceiver with distributed dual-loop compensation (DDLC) for VDDQ-ripple suppression and dynamic duty-cycle calibration (DDCC) for robust clocking is presented. The DDLC locally regulates VDDQ with a shared low- power LDO, reducing the required decoupling capacitor by 91.4%, while improving horizontal and vertical eye margins by 61% and 36%. Demonstrated on five channels, the proposed DDLC scales naturally to larger DQ counts for high-density memories. As AI and chiplet technologies proliferate, the demand for high efficiency, high density, and high-speed data transmission between processors and memory continues to surge. Advanced packaging technologies such as silicon bridges, interposers, and through-silicon vias (TSVs) mitigate channel loss and ease equalization requirements [1-8]. While these signal integrity (SI) challenges are mitigated, power integrity (PI), impacted by IR drops, is
Yuchen He*1, Yunbin Luo*1, Yunzhengmao Wang*1, Tengyue Yi2, Chen Jiang1, Chixiao Chen1, Qi Liu1, Ming Liu1, Wenning Jiang1
Fudan University, Shanghai, China, 2ZhangJiang Laboratory, Shanghai, China