A CMOS Hybrid Common-Gate Current-Integrating Sampler with >37dB SNDR Across 51GHz BW in a 128GS/s Front-End

📋 论文概要

本文提出了一种CMOS混合共栅电流积分采样器，用于解决宽带ADC前端中的线性度、带宽和抖动限制。该前端采用混合共栅V-I转换器、变压器耦合电感峰化和自动功率门控保持缓冲器，在51GHz带宽内实现了超过37dB的SNDR，并在128GS/s前端中展示了优越的SNDRBW-性能。

💡 主要创新点

• 提出混合共栅V-I转换器，结合变压器耦合电感峰化技术，显著提升带宽和线性度。
• 采用自动功率门控保持缓冲器，降低功耗并改善采样保持性能。
• 在128GS/s前端中实现>37dB SNDR across 51GHz BW，优于先前报道的宽带采样器/ADC。

🏷 关键词

📄 原文摘要

Abstract This work proposes a CMOS hybrid common-gate current integrating sampler to address linearity, BW, and jitter limitations in prior wideband ADC front-ends. The front-end employs a hybrid common-gate V-I converter, transformer-coupled inductive peaking, and an automatic power-gating hold buffer, enabling 48.1dB SFDR and 38.6dB SNDR near its 52GHz BW-3dB. This work demonstrates superior SNDRBW- (measured near BW3dB), outperforming prior samplers/ADCs reported in ISSCC/JSSC/VLSI with BW>30GHz. The rapid expansion of AI applications greatly increases the demand for wireline links. Longreach receivers often adopt the ADC-DSP architecture, where ADCs enable flexible digital equalization. The ADC needs to have wide BW, low noise, and high linearity, all of which are limited by the front-end sample-and-hold (S/H) circuit [1-8]. Figure 21.8.1 top-left shows a conventional CMOS S/H design. Despite using a T-coil, the high loss of the CMOS

👥 作者与机构

Jun Dai1, Yi Zhong1, Yunsong Tao1, Aodong Zhang1, Mingtao Zhan1, Hao Zhang2, Lu Jie1, Nan Sun1

Tsinghua University, Beijing, China, 2Magnichip, Nanjing, China