⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一种用于多分支存储器接口的单向自训练方案，通过直接从单脉冲响应导出判决反馈均衡器（DFE）系数，无需控制器交互，有效均衡码间干扰（ISI）和反射。该接收器在40nm CMOS工艺下实现8Gb/s/pin速率，总吞吐量102.4Gb/s，在4分支通道中重新打开闭眼，误码率低于10^-12，能效0.64pJ/b，硬件开销仅6.74%。
8Gb/s/pin receiver with a one-way self-training scheme for highlyreflective multi-drop memory interfaces. DFE tap coefficients are directly derived from a single-pulse response, eliminating controller interaction during training. Implemented in 40nm CMOS, the receiver reopens a closed eye in a 4-drop channel at BER < 10-12. Reusing existing circuitry, the design achieves 102.4Gb/s throughput with only a 6.74% hardware overhead and a 0.64pJ/b energy efficiency. AI and data-center applications demand memory systems with both high capacity and unprecedented performance, driving their evolution. Interface topologies evolved into distinct regimes: performance-critical systems such as GDDR and LPDDR utilize point-topoint connections for maximum signal integrity. Even mainstream DRAM, which traditionally
Ji-Won Moon1, Taehyeon Kim1, Minwook Kim1, Hyeonwoo Seong1, Jewon Lee1, Jeongbin Park1, Dongjun Park1, Jaehoon Lee1, Jung-June Park2,
Chiweon Yoon2, Jae-Yoon Sim1, Seon-Kyoo Lee1 Pohang University of Science and Technology, Pohang, Korea, 2Samsung Electronics, Hwaseong, Korea 1 Abstract This paper presents a 12