AI / ML

A 28nm 192.3TFLOPS/W Accurate/Approximate Dual-Mode-Transpose Digital 6T-SRAM CIM Macro for Floating-Point Edge Training and Inference connection using the 3rd-metal layer and connect the corresponding diagonal in the 4th layer; the row connection is in the 5th layer. This method circumvents the need for numerous MAC circuits and read ports as is the case for previous T-CIM works [7,8], resulting in a reduction in area and power consumption.

A 51.6TFLOPs/W Full-Datapath CIM Macro Approaching Sparsity Bound and <2-30 Loss for Compound AI

A 28nm 17.83-to-62.84TFLOPS/W Broadcast-Alignment Floating-Point CIM Macro with Non-Two’s-Complement MAC for CNNs and Transformers

A 16nm 216kb, 188.4TOPS/W and 133.5TFLOPS/W Microscaling Multi-Mode Gain-Cell CIM Macro Edge-AI Devices loss of accuracy. In HV mode, the M2-IPU aligns INM based on both ∆PDE and ∆PDSS, with extra shifting in INM from ∆PDSS, which increases INM sparsity, further enhancing EEF. In phase 2 (Ph2), the OUT-PRO processes the activation function of the M2-CIM outputs and

A 22nm 104.5TOPS/W µ-NMC-∆-IMC Heterogeneous STT-MRAM CIM Macro for Noise-Tolerant Bayesian Neural Networks

An 8.62μW 75dB-DRSoC End-to-End Spoken-LanguageUnderstanding SoC with Channel-Level AGC and Temporal-Sparsity-Aware Streaming-Mode RNN

A 0.22mm2 161nW Noise-Robust Voice-Activity Detection Using Information-Aware Data Compression and Neuromorphic Spatial-Temporal Feature Extraction

A 0.35V 0.367TOPS/W Image Sensor with 3-Layer Optical-Electronic Hybrid Convolutional Neural Network

A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process

A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices

A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing

A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC

A 818-4094TOPS/W Capacitor-Reconfigured CIM Macro for Unified Acceleration of CNNs and Transformers Kentaro Yoshioka

A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell

A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs

A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-CellComputing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices

A 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for High-Accuracy AI Applications and denotes early 01 or 10 change. It uses XOR and a leading-one detector if RA/RB with different signs. BRPU reduces the regime processing energy by 68%.

A Miniature Neural Interface Implant with a 95% Charging Efficiency Optical Stimulator and an 81.9dB SNDR ΔΣM-Based Recording Frontend

A Two-Electrode Bio-Impedance Readout IC with ComplexDomain Noise-Correlated Baseline Cancellation Supporting Sinusoidal Excitation

An Adhesive Interposer-Based Reconfigurable Multi-Sensor Patch Interface with On-Chip Application Tunable Time-Domain Feature Extraction

A Millimetric Batteryless Biosensing and Stimulating Implant with Magnetoelectric Power Transfer and 0.9pJ/b PWM Backscatter

Closed-Loop 100-Channel Highly-Scalable Retinal Implant with 1.02μW Analog ED-Based Adaptive-Threshold Spike Detection and Poisson-Coded Temporally Distributed Optogenetic Stimulation

A Multi-Loop Neuromodulation Chipset Network with Frequency-Interleaving Front-End and Explainable AI for Memory Studies in Freely Behaving Monkeys

MiBMI: A 192/512-Channel 2.46mm2 Miniaturized Brain-Machine Interface Chipset Enabling 31-Class Brain-to-Text Conversion Through Distinctive Neural Codes

A Sub-1µJ/class Headset-Integrated Mind Imagery and Control SoC for VR/MR Applications with Teacher-Student CNN and General-Purpose Instruction Set Architecture

A Hybrid Recording System with 10kHz-BW 630mVPP 84.6dB-SNDR 173.3dB-FOMSNDR and 5kHz-BW 114dB-DR for Simultaneous ExG and Biocurrent Acquisition

A 2.7ps-ToF-Resolution and 12.5mW Frequency-domain NIRS Readout IC with Dynamic Light Sensing Frontend and Cross-Coupling-Free Inter-Stabilized Data Converter

A High-Accuracy and Energy-Efficient Zero-Shot-Retraining Seizure-Detection Processor with Hybrid-Feature-Driven Adaptive Processing and Learning-Based Adaptive Channel Selection

An Ultra-Compact 28GHz Doherty Power Amplifier with an Asymmetrically-Coupled-Transformer Output Combiner

Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing

A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing

Space-Mate: A 303.5mW Real-Time Sparse Mixture-ofExperts-Based NeRF-SLAM Processor for Mobile Spatial Computing

NeuGPU: A 18.5mJ/Iter Neural-Graphics Processing Unit for Instant-Modeling and Real-Time Rendering with SegmentedHashing Architecture

LSPU: A Fully Integrated Real-Time LiDAR-SLAM SoC with Point-Neural-Network Segmentation and Multi-Level kNN Acceleration

C-Transformer: A 2.6-18.1μJ/Token Homogeneous DNN-Transformer/Spiking-Transformer Processor with Big-Little Network and Implicit Weight Generation for Large Language Models

A 28nm Physics Computing Unit Supporting Emerging Physics-Informed Neural Network and Finite Element Method for Real-Time Scientific Computing on Edge Devices

A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications

A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models

NVE: A 3nm 23.2TOPS/W 12b-Digital-CIM-Based Neural Engine for High-Resolution Visual-Quality Enhancement on Smart Devices

IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip

A 1mW Always-on Computer Vision Deep Learning Neural Decision Processor

CTLE-Ising: A 1440-Spin Continuous-Time Latch-Based Ising Machine with One-Shot Fully-Parallel Spin Updates Featuring Equalization of Spin States

A 22nm Delta-Sigma Computing-In-Memory (∆ΣCIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing

CV-CIM: A 28nm XOR-Derived Similarity-Aware Computation-in-Memory for Cost-Volume Construction

A 70.85–86.27TOPS/W PVT-Insensitive 8b Word-Wise ACIM with Post-Processing Relaxation

A 28nm Horizontal-Weight-Shift and Vertical-Feature-ShiftBased Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks

A 4nm 6163-TOPS/W/b 4790-TOPS/mm2/b SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update disabled, to save power, in 8b mode. The INWIDTH[1:0] bus controls the XIN width: 00 for 8b, 01 for 12b, and 10 for 16b modes. To support a signed format with width flexibility, the first 4 cycles are signed 4b operations and the rest of the cycles are unsigned 4b operations, regardless of INWIDTH.

A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-PointComputing-Unit and Double-Bit 6T-SRAM Computing-inMemory Macro for Floating-Point CNNs

A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices