A 20-Gb/s/pin 0.0024-mm2 Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces

📋 论文概要

该论文提出了一种采用单端DECS收发器的20 Gb/s/pin接口，通过无CDR的自切片和自动解串技术，提高了对数据抖动的容忍度，并减少了时钟和数据路径失配的影响。

💡 主要创新点

• 提出CDR-less自切片/自动解串技术，消除传统CDR导致的时钟与数据路径失配问题。
• 采用单端DECS结构，利用参考时钟代替参考电压，改善电源抑制并抑制共模噪声。

🏷 关键词

📄 原文摘要

Samsung Electronics, Hwaseong, Korea SSC DECS input, the resulting clock and data paths are equally matched and the impact of the RX SN on the RX performance is minimized. In a conventional RX the sampling clock is generated by a CDR; hence, the signal path is not well matched to the data path and clock jitter caused by SN significantly degrades RX performance. In addition, the SSC has good power supply rejection, since a reference clock is used as an input instead of a reference voltage. Similar to differential signaling, the DECS helps subtracting the common-mode noise. Supply-induced reference-voltage noise for a conventional SE comparator further degrades performance. 1 2 In massively parallel short-reach (SR) interfaces [2-5], thousands of I/Os communicate through many low-loss parallel interconnects (Fig. 28.7.1). Due to the large number of I/Os, each transceiver (TRX) design must fit within a small area and be energy-efficient.

👥 作者与机构

Jaeyoung Seo1, Sooeun Lee2, Myungguk Lee1, Changjae Moon1, Byungsub Kim1

Pohang University of Science and Technology, Pohang, Korea