⚡ 本页包含 AI 生成的分析内容，仅供参考
该论文提出了一种65nm工艺的脉动神经CPU处理器，用于结合深度学习与通用计算，通过提高PE利用率和数据局部性来增强端到端性能，解决了深度学习任务中预处理、数据对齐和内存移动导致的执行时间瓶颈问题。
network (DNN) accelerators, few works have targeted improving the end-to-end performance of deeplearning tasks, where inter-layer pre/post-processing, data alignment and data movement across memory and processing units often dominate the execution time. An improvement to the end-to-end computation requires cohesive cooperation between the accelerator and the CPU with highly efficient data flow management. Figure 15.2.1 shows the most commonly used heterogeneous architecture, containing a CPU core and an accelerator with data communication managed by a DMA engine. However, there remain the challenges of low utilization of PE cores and large latency due to the CPU workload and data movement across processing cores [1-4]. As shown in Fig. 15.2.1, in an end-toend deep learning task, the accelerator is often utilized at only 30-50% with the rest of
Utilization, High Data Locality and Enhanced End-to-End, Performance
Yuhao Ju, Jie Gu Northwestern University, Evanston, IL Despite recent progress on building highly efficient deep neural