A 1V 32.1dBm 92-to-102GHz Power Amplifier with a Scalable 128-to-1 Power Combiner Achieving 15% Peak PAE in a 65nm Bulk CMOS Process

📋 论文概要

本文提出了一款在65nm bulk CMOS工艺中实现的1V供电、92-102GHz功率放大器，采用可扩展的128-to-1功率合成器，实现了32.1dBm输出功率和15%峰值PAE。该设计解决了毫米波频段低电压下高输出功率和高效率的挑战。

💡 主要创新点

• 提出了可扩展的128-to-1片上功率合成器结构，在低电压下实现高输出功率
• 在65nm bulk CMOS工艺中实现了W波段（92-102GHz）功率放大器，达到32.1dBm输出功率和15%峰值PAE

🏷 关键词

📄 原文摘要

increase of the speed and data-rate achieved by 5G. A major challenge in 6G is to provide a large transmitter output power (Pout) with high energy efficiency and linearity from a limited supply voltage to overcome high path loss, given the inevitable exploitation of higher millimeter-wave (mm-wave) frequencies (W-band and above) [1-5]. The low breakdown voltage of silicon-based processes limits the use of “vertical” power-boost techniques, such as using higher voltages and stacking more transistors. Therefore, the “horizontal” on-chip power-combine technique has attracted more attention. Due to the poor passive efficiency and the physical implementation difficulty, power-combine techniques suitable for high mm-wave systems are scarce. Most of the PAs adopt zerodegree power-combine technique at W-band [3-5]. However, the nature of the

👥 作者与机构

Wei Zhu, Jiawen Wang, Ruitao Wang, Jian Zhang, Chenguang Li, Sen Yin, Yan Wang

Tsinghua University, Beijing, China The sixth-generation (6G) wireless communication is emerging and continuous the