A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer

📋 论文概要

本文提出了一种工作在triode区的模拟LDO，采用分布式增益增强和动态负载电流跟踪技术，在Intel 4工艺下实现0.76V输入电压和4A输出电流，旨在解决低 dropout 电压下高PSR的需求。

💡 主要创新点

• 采用triode区工作而非传统饱和区，以减小dropout电压
• 分布式增益增强结构提升环路增益和PSR
• 动态负载电流跟踪技术改善瞬态响应和负载调节

🏷 关键词

📄 原文摘要

compute/memory and analog/mixed-signal circuits such as SerDes transceivers, RF/wireless front-end, PLLs, sensors, etc. On-chip low-dropout regulators (LDOs) isolate the input Vin noise from switching DC-DC converters powering the digital blocks (Fig. 30.4.1) and provide high power-supply rejection (PSR) to the noise-sensitive analog/mixed-signal circuits by modulating the small-signal output resistance (Ro) of the power FET in the saturation region. Therefore, the minimum dropout (DO) voltage must be larger than the necessary gate overdrive (OV). While larger DO enables higher Ro and better PSR, it degrades the LDO power conversion efficiency (PCE). Using larger power FETs can reduce OV and DO for a target Imax, but at the cost of more die area. Therefore, LDO designs that provide

👥 作者与机构

Xiaosen Liu, Harish Krishnamurthy, Renzhi Liu, Krishnan Ravichandran,

Zakir Ahmed, Nachiket Desai, Nicolas Butzen, James Tschanz, Vivek De Intel, Portland, OR Complex SoCs in nanoscale CMOS integrate a variety of digital