A 22nm 0.84mm2 BLE Transceiver with Self IQ-Phase Correction Achieving 39dB Image Rejection and On-Chip Antenna Impedance Tuning

📋 论文概要

本文提出了一款采用22nm CMOS工艺、面积为0.84mm²的BLE收发器，通过自IQ相位校正技术实现了39dB的镜像抑制，并集成了片上天线阻抗匹配网络。该设计旨在降低物联网无线传感器节点的成本和功耗。

💡 主要创新点

• 提出自IQ相位校正技术，有效提升镜像抑制性能至39dB。
• 集成片上天线阻抗匹配网络（AIT），为RX和TX独立提供最佳阻抗匹配，并利用π型LPF抑制TX谐波。
• 在22nm工艺下实现0.84mm²的小面积，适合低功耗物联网应用。

🏷 关键词

📄 原文摘要

Figure 24.4.4 shows the proposed AIT providing optimum impedance matching for RX Kenichi Shibata, Hiroaki Matsui, Hironori Asano, Yuichi Kusaka, Keisuke Ueda, and TX independently with a wide impedance tunability. In TX mode, CTX, LTX, and CP Noriaki Matsuno, Hisayasu Sato also form a π-shaped LPF that suppresses the third- or higher-order harmonics. The RX Renesas Electronics, Tokyo, Japan The IoT crucially requires a large number of low-cost and low-power wireless sensor nodes. BLE is a strong candidate for their wireless interface. Much effort has been made in prior BLE transceivers to reduce power consumption by employing Sliding-IF (SIF) architecture in RX [1,3,4,6] or the stacked LO buffer in Low-IF architecture [2]. However, prior arts cannot realize low power and small area at the same time. As the SIF architecture needs RF notch filters to suppress image response, it requires multiple onchip inductors resulting in large area. On the other hand, the Low-IF architecture requires

👥 作者与机构

reduce area and power consumption. In order to make 50%-duty LO signals for the TXPA and the PLL, we use NORs with latch function in Fig. 24.4.2. The NOR is much lower, power than an additional 50%-duty divider.