DIANA: An End-to-End Energy-Efficient DIgital and ANAlog Hybrid Neural Network SoC

📋 论文概要

提出了一种端到端能量高效的数字和模拟混合神经网络SoC（DIANA），用于边缘设备上的高效矩阵向量乘法。通过结合数字和模拟计算的优势，解决了传统单一架构在能效和精度之间的权衡问题。

💡 主要创新点

• 数字与模拟混合架构，在保持精度的同时大幅提升能效。
• 端到端能量优化，从算法到电路层面协同设计。
• 针对边缘推理场景，实现高吞吐量和低功耗的神经网络加速。

🏷 关键词

📄 原文摘要

Giuseppe M. Sarda1,2, Vikram Jain1, Man Shi1, Qilin Zheng1, Sebastian Giraldo1, Peter Vrancx2, Jonas Doevenspeck2, Debjyoti Bhattacharjee2, Stefan Cosemans2, Arindam Mallik2, Peter Debacker2, Diederik Verkest2, Marian Verhelst1,2 KU Leuven, Leuven, Belgium; 2imec, Leuven, Belgium *Equally Credited Authors (ECAs) 1 Energy-efficient matrix-vector multiplications (MVMs) are key to bringing neural network (NN) inference to edge devices. This has led to a wide range of state-of-the-art MVM acceleration chips, which fall into two categories: 1) Digital NN accelerators [1-2], constituting widely parallel multiply-accumulate (MAC) arrays at medium (typically 48b) precision. 2) Analog in-memory compute (AiMC) NN accelerators [3-4], which enable much higher energy efficiencies and throughput per unit area at the cost of a reduced computational precision, reduced dataflow flexibility, and resulting reduced mapping

👥 作者与机构

Kodai Ueyoshi*1, Ioannis A. Papistas*2, Pouya Houshmand1,