3D V-Cache: The Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU

📋 论文概要

该论文介绍了一种通过混合键合技术将64MB堆叠缓存附加到7nm x86-64 CPU上的3D V-Cache实现。它扩展了Zen3处理器的L3缓存从32MB到96MB，提供高达2TB/s带宽和平均15%的游戏性能提升，同时描述了混合键合技术、架构设计、DFT及实测结果。

💡 主要创新点

• 采用混合键合（Hybrid Bonding）技术实现3D堆叠缓存，相比传统μBump方案显著提升带宽和能效。
• 将片上L3缓存容量从32MB扩展至96MB，通过增加缓存层次提升处理器性能，尤其针对游戏场景。
• 详细介绍了3D堆叠缓存的架构设计、DFT（可测试性设计）以及实测性能结果，为高性能处理器缓存扩展提供了完整方案。

🏷 关键词

📄 原文摘要

3D stacked product that attaches additional cache onto a high-performance processor through hybrid bonding, a technology that offers significant bandwidth and power benefits over state-of-the-art uBump based approaches. V-Cache expands Zen3’s on-die L3 Cache from 32MB to 96MB, providing up to 2TB/s of bandwidth and 15% average gaming performance uplift. This paper describes the hybrid bonding technology components, provides insight into the V-Cache’s architecture and design, discusses the associated DFT implications, and offers measured performance results. This paper is presentation-only. 428 • 2022 IEEE International Solid-State Circuits Conference 978-1-6654-2800-2/22/$31.00 ©2022 IEEE

👥 作者与机构

John Wuu1, Rahul Agarwal2, Michael Ciraula1, Carl Dietz1, Brett Johnson1,

Dave Johnson1, Russell Schreiber3, Raja Swaminathan3, Will Walker1, Samuel Naffziger1 AMD, Fort Collins, CO AMD, Santa Clara, CA 3 AMD, Austin, TX 1 2 AMD’s V-Cache is a