ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory

📋 论文概要

提出一种名为ARCHON的5比特变化容忍模拟CNN处理器，通过模拟神经元计算单元解决传统模拟MAC频繁使用ADC/DAC的高能耗问题。实现了332.7TOPS/W的极高能效。

💡 主要创新点

• 设计了模拟神经元计算单元，减少中间特征图在模拟与数字域之间的频繁转换。
• 采用变化容忍技术，提高模拟电路在工艺变化下的可靠性。

🏷 关键词

📄 原文摘要

One of the notable trends in convolutional neural network (CNN) processor architecture is to embrace analog hardware to improve energy efficiency in performing multiply-andaccumulate (MAC). Prior works investigated charge redistribution in a capacitor array [4, 5], phase accumulation in oscillators [2, 6], and the integrator in a delta-sigma modulator [3]. However, these works suffer from two critical challenges. First, they all need frequent use of ADCs and DACs to store and access the large intermediate computation results, i.e. feature maps, to and from the digital SRAM. The energy consumption of such data conversion severely limits the overall energy efficiency. To mitigate it, [1] uses analog memory but only for temporary data and it still requires a large amount of data conversion for computing multiple layers of a CNN model. Second, analog circuits including analog memory inherently exhibit non-negligible variability.

👥 作者与机构

Jin-O Seo1, Mingoo Seok2, SeongHwan Cho1

KAIST, Daejeon, Korea; 2Columbia University, New York, NY