A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices

📋 论文概要

该论文提出了一种基于28nm工艺的1Mb时域计算内存（Time-Domain Computing-in-Memory）6T-SRAM宏，用于边缘AI设备的8位乘累加（MAC）操作。该宏实现了6.6ns的延迟、1241GOPS的吞吐量和37.01TOPS/W的能效，解决了传统SRAM-CIM能效和速度的平衡问题。

💡 主要创新点

• 采用时域计算方式代替传统模拟或数字域计算，提升能效并降低对模拟电路精度的依赖。
• 使用6T-SRAM单元实现内存计算，相比标准单元或模拟电路更节省面积，适合大规模集成。
• 通过优化的电路和架构设计，在1Mb容量下实现了1241GOPS的高吞吐量和37.01TOPS/W的能效，同时延迟仅为6.6ns。

🏷 关键词

📄 原文摘要

Jin-Sheng Ren1, Fu-Chun Chang1, Yuan Wu1, Ho-Yu Chen1, Chen-Hsun Lin1, Hsu-Ming Hsiao2, Sih-Han Li2, Shyh-Shyuan Sheu2, Shih-Chieh Chang2, Wei-Chung Lo2, Chung-Chuan Lo1, Ren-Shuo Liu1, Chih-Cheng Hsieh1, Kea-Tiong Tang1, Chih-I Wu2, Meng-Fan Chang1 National Tsing Hua University, Hsinchu, Taiwan 2 Industrial Technology Research Institute, Hsinchu, Taiwan 1 *Equally Credited Authors (ECAs) SRAM-based computing in memory (SRAM-CIM) is an attractive approach to improve the energy efficiency (EF) of edge-AI devices performing multiply-and-accumulate (MAC) operations. SRAM-CIM with a large memory capacity enhances EF by reducing data movement between system memory and compute functions. High-precision inputs (IN), weights (W) and outputs (OUT) are essential to deliver sufficient inference accuracy using SRAM-CIM. These devices must also enable a short compute latency (tAC) and a high multiply-accumulate throughput (TP) to achieve a fast system-level response time

👥 作者与机构

Ping-Chun Wu*1, Jian-Wei Su*2, Yen-Lin Chung1, Li-Yang Hong1,