A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computingin-Memory Macro Supporting Wide-Range Dynamic-VoltageFrequency Scaling and Simultaneous MAC and Write Operations

📋 论文概要

该论文提出了一种5nm全数字计算存储一体（CIM）宏，解决了模拟CIM精度不足的问题，实现了254 TOPS/W的能效和221 TOPS/mm2的面积效率，并支持宽范围动态电压频率缩放。

💡 主要创新点

• 采用全数字CIM架构，避免了模拟CIM的精度损失，同时保持高能效。
• 支持宽范围动态电压频率缩放（DVFS），适应不同工作负载。
• 在5nm工艺下实现了领先的TOPS/W和TOPS/mm2指标。

🏷 关键词

📄 原文摘要

Rawan Naous2, Chao-Kai Chuang1, Takeshi Hashizume3, Dar Sun1, Chia-Fu Lee1, Kerem Akarvardar2, Saman Adham4, Tan-Li Chou1, Mahmut Ersin Sinangil2, Yih Wang1, Yu-Der Chih1, Yen-Huei Chen1, Hung-Jen Liao1, Tsung-Yung Jonathan Chang1 TSMC, Hsinchu, Taiwan TSMC, San Jose, CA 3 TSMC, Yokohama, Japan 4 TSMC, Austin, TX 1 2 Computing-in-memory (CIM) is being widely explored to minimize power consumption in data movement and multiply-and-accumulate (MAC) for edge-AI devices. Although most prior work focuses on analog-based CIM (ACIM) to leverage the BL charge/discharge operation, the lack of accuracy caused by transistor variation and the ADC is an issue [1-3]. In contrast, a digital-based CIM (DCIM) approach realizes enough accuracy and flexibility for various input and weight bit widths [4, while also benefiting from technology scaling. This paper proposes a 64kb DCIM macro using a one-read and

👥 作者与机构

Hidehiro Fujiwara1, Haruki Mori1, Wei-Chang Zhao1, Mei-Chen Chuang1,